The aim of this work is to present a digital implementation of a water level controller for a pressurized water reactor (PWR) using FPGA architectures. The application of FPGA is widely diffused in the conventional industry, whereas some issues have to be solved for a direct use of this architecture in the nuclear field. Possible advantages and limitations of using an advanced, digital hardware-based controller on a pressurized water reactor are here considered. The water level controller has been modeled as a feedback linearizing controller with a PI action and sliding mode estimator. The digital implementation consisted of several phases: a discrete-time, floating-point version converted to a fixed-point one; a conversion of the controller into the hardware description language (VHDL), and the synthesis for the FPGA; a final connection of the controller in the SimulinkR model to the actual hardware. The feasibility of such an approach has been shown, and the results have been validated against a PWR model using the hardware-in-the-loop technique.
Water level controller for a pressurized water reactor: Digital implementation on FPGA
Cappelli, M.;
2019-01-01
Abstract
The aim of this work is to present a digital implementation of a water level controller for a pressurized water reactor (PWR) using FPGA architectures. The application of FPGA is widely diffused in the conventional industry, whereas some issues have to be solved for a direct use of this architecture in the nuclear field. Possible advantages and limitations of using an advanced, digital hardware-based controller on a pressurized water reactor are here considered. The water level controller has been modeled as a feedback linearizing controller with a PI action and sliding mode estimator. The digital implementation consisted of several phases: a discrete-time, floating-point version converted to a fixed-point one; a conversion of the controller into the hardware description language (VHDL), and the synthesis for the FPGA; a final connection of the controller in the SimulinkR model to the actual hardware. The feasibility of such an approach has been shown, and the results have been validated against a PWR model using the hardware-in-the-loop technique.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
