To achieve the aim of the international thermonuclear experimental reactor (ITER) radial neutron camera diagnostic, the data acquisition prototype must be compliant with a sustained 2-MHz peak event per each channel. The data are acquired and processed using an IPFN FPGA Mezzanine Card (FMC-AD2-1600) with two digitizer channels of 12-bit resolution and a sampling rate up to 1.6 GSamples/s mounted in an peripheral component interconnect express (PCIe) evaluation board from Xilinx (KC705) installed in the host PC. The acquired data in the event-based data path are streamed to the host through the PCIe × 8 direct memory access with a maximum data throughput per channel 0.5 GB/s of raw data (event base), 1 GB/s per digitizer, and up to 1.6 GB/s in continuous mode. The prototype architecture comprises a host PC with two KC705 modules and four channels, producing up to 2 GB/s in event mode and up to 3.2 GB/s in continuous mode. To reduce the produced data throughput from host to ITER archiving system, the real-time data compression was evaluated using the LZ4 lossless compression algorithm, which provides compression speed up to 400 MB/s per core. This paper presents the architecture, implementation, and test of the parallel real-time data compression system running in multiple isolated cores. The average space saving and the performance results for long-term acquisitions up to 30 min, using different data block sizes and different number of CPUs, are also presented.
Real-Time Data Compression for Data Acquisition Systems Applied to the ITER Radial Neutron Camera
Riva M.;Pollastrone F.;Centioli C.;Marocco D.;Esposito B.;
2019-01-01
Abstract
To achieve the aim of the international thermonuclear experimental reactor (ITER) radial neutron camera diagnostic, the data acquisition prototype must be compliant with a sustained 2-MHz peak event per each channel. The data are acquired and processed using an IPFN FPGA Mezzanine Card (FMC-AD2-1600) with two digitizer channels of 12-bit resolution and a sampling rate up to 1.6 GSamples/s mounted in an peripheral component interconnect express (PCIe) evaluation board from Xilinx (KC705) installed in the host PC. The acquired data in the event-based data path are streamed to the host through the PCIe × 8 direct memory access with a maximum data throughput per channel 0.5 GB/s of raw data (event base), 1 GB/s per digitizer, and up to 1.6 GB/s in continuous mode. The prototype architecture comprises a host PC with two KC705 modules and four channels, producing up to 2 GB/s in event mode and up to 3.2 GB/s in continuous mode. To reduce the produced data throughput from host to ITER archiving system, the real-time data compression was evaluated using the LZ4 lossless compression algorithm, which provides compression speed up to 400 MB/s per core. This paper presents the architecture, implementation, and test of the parallel real-time data compression system running in multiple isolated cores. The average space saving and the performance results for long-term acquisitions up to 30 min, using different data block sizes and different number of CPUs, are also presented.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
